The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with a gate dielectric of metal oxide for relatively high thickness of the gate dielectric to minimize tunneling current through the gate dielectric.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (SiN), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
Conventionally, the gate dielectric 116 for the MOSFET 100 is typically comprised of silicon dioxide (SiO2), and the gate electrode 118 is typically comprised of polysilicon. As the channel length and width dimensions of the MOSFET 100 are scaled down for enhanced speed performance, the thicknesses of the gate dielectric 116 and the gate electrode 118 are also correspondingly scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as the channel length and width dimensions of the MOSFET 100 are scaled down to tens of nanometers, the thickness of the gate dielectric 116 is also scaled down to tens of angstroms when the gate dielectric 116 is comprised of silicon dioxide (SiO2). With such a thin gate dielectric 116, charge carriers easily tunnel through the gate dielectric 116, as known to one of ordinary skill in the art of integrated circuit fabrication.
When charge carriers tunnel through the gate dielectric 116, gate leakage current undesirably increases resulting in increased static power dissipation and even circuit malfunction. In addition, with charge carriers tunneling through the gate dielectric 116, decreased charge carrier accumulation in the channel of the MOSFET may result in undesirable increase in resistance through the channel of the MOSFET. Furthermore, with the thin gate dielectric 116, the charge accumulation at the gate electrode 118 causes an undesirable increase in charge carrier scattering at the surface of the channel of the MOSFET 100. Such increase in charge carrier scattering in turn results in higher resistance through the channel of the MOSFET.
In light of these disadvantages of the thin gate dielectric 116 when the gate dielectric 116 is comprised of silicon dioxide (SiO2), a gate dielectric having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) (i.e., a high dielectric constant material) is used for a field effect transistor having scaled down dimensions of tens of nanometers. A dielectric material having a higher dielectric constant has higher thickness for achieving the same capacitance. Thus, when the gate dielectric is comprised of a high dielectric constant material, the gate dielectric has a higher thickness (hundreds of angstroms) than when the gate dielectric is comprised of silicon dioxide (SiO2) (tens of angstroms), for field effect transistors having scaled down dimensions of tens of nanometers.
The gate dielectric with high dielectric constant has higher thickness to minimize charge carrier tunneling through the gate dielectric for field effect transistors having scaled down dimensions of tens of nanometers. Charge carrier tunneling through the gate dielectric is minimized exponentially by the thickness of the gate dielectric. Examples of dielectric materials with high dielectric constant include metal oxides such as aluminum oxide (Al2O3), titanium dioxide (TiO2), tantalum oxide (Ta2O5), or zirconium dioxide (ZrO2).
Such dielectric material are usually deposited or sputtered onto the semiconductor substrate in the prior art. However, with the deposition and sputtering processes of the prior art, the uniformity of thickness of such dielectric material for formation of gate dielectrics having scaled down dimensions of hundreds of angstroms is typically unacceptable. In addition, the metal oxide is typically difficult to etch. For example, in a wet etch process, metal residue from the etched metal oxide may undesirably contaminate the semiconductor substrate. Furthermore, a metal oxide structure having high quality interfacial adhesion to the channel region of the MOSFET of the semiconductor substrate is desired.
Thus, a mechanism is desired for effectively fabricating a metal oxide structure having relatively high thickness on the semiconductor substrate for use as a gate dielectric of a field effect transistor having scaled down dimensions of tens of nanometers to minimize charge carrier tunneling through the gate dielectric.
Accordingly, in a general aspect of the present invention, a metal oxide structure is fabricated by forming an opening on top of a layer of metal and with localized thermal oxidation of the layer of metal exposed at the opening. In addition, a dopant, such as nitrogen ions are implanted into the semiconductor substrate near the layer of metal before formation of the metal oxide structure to promote strong interfacial adhesion of the metal oxide structure to the semiconductor substrate.
In one embodiment of the present invention, in a method for fabricating a metal oxide structure on a semiconductor substrate, an active device area is formed to be surrounded by at least one STI (shallow trench isolation) structure in the semiconductor substrate. A layer of metal is deposited on the semiconductor substrate, and the layer of metal contacts the active device area of the semiconductor substrate. A layer of oxygen blocking material is deposited on the layer of metal, and an opening is etched through the layer of oxygen blocking material to expose an area of the layer of metal on top of the active device area. An interfacial dopant is implanted through the layer of metal to the semiconductor substrate adjacent the layer of metal in the area of the opening where the layer of metal is exposed.
A thermal oxidation process is performed to form a metal oxide structure from reaction of oxygen with the area of the opening where the layer of metal is exposed. A thickness of the metal oxide structure is determined by a thickness of the layer of metal, and the layer of oxygen blocking material prevents contact of oxygen with the layer of metal such that the metal oxide structure is formed localized at the area of the opening where the layer of metal is exposed. The interfacial dopant implanted into the semiconductor substrate adjacent the layer of metal promotes adhesion of the metal oxide structure to the semiconductor substrate.
In this manner, the metal oxide structure is formed by localized thermal oxidation of the layer of metal such that a deposition or sputtering process or an etching process is not necessary for formation of the metal oxide structure. In addition, the thickness of the metal oxide structure is determined by controlling the thickness of the layer of metal used for forming the metal oxide structure.
In another embodiment of the present invention, a layer of conductive material is deposited to fill the opening of the layer of oxygen blocking material. The layer of conductive material is deposited over the layer of oxygen blocking material. The layer of conductive material is polished down over the layer of oxygen blocking material until the layer of oxygen blocking material is exposed. The conductive material that is contained within the opening of the layer of oxygen blocking material and that is disposed over the metal oxide structure remains to form a gate structure of a field effect transistor, and the metal oxide structure forms a gate dielectric of the field effect transistor. Any exposed regions of the oxygen blocking material is etched away such that sidewalls of the gate structure of the conductive material are exposed. Also, any exposed regions of the layer of metal is etched away such that the sidewalls of the gate dielectric of the metal oxide structure are exposed.
The present invention may be used to particular advantage when the interfacial dopant is comprised of nitrogen ions, when the layer of oxygen blocking material is comprised of silicon nitride (SiN), and when the metal oxide structure is comprised of one of aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2) having a thickness in a range of from about 150 xc3x85 (angstroms) to about 200 xc3x85 (angstroms).
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.